Hi. I'm Ravi Mahajan, Intel Fellow, and I'm here to talk to you about
trends in packaging. If you're the person who reads The Buzz, reads the Trade Press, you will notice there is
tremendous amount of buzz about this whole business of
microelectronics packaging. There was a product Intel
announced called Ponte Vecchio. This product has more than
100 billion transistors. It has 47 active tiles that
are packaged together. It takes IP implemented on five different
processes, combines, compute memory through a very complex integrate that goes all over the lateral of the package
as well as the vertical. This enables leadership products that have leadership
silicon technology, leadership performance,
leadership packaging, and they scaled capacity
when implemented in a HPC supercomputer device, and gives unprecedented
performance. In fact, packaging is so
important that it even made it into a report that
was submitted to the White House last year. This was intended to
show that this is a crucial piece of
enabling compute, and performance moving forward. By the end of this video, you should be able to
understand the trends that have driven the historical evolution of microelectronics packaging, and why it is so crucial for the future of
microelectronics systems. This picture, by the way,
describes revolutions. Packaging over the last few
decades has seen very quiet, but highly influential
revolutions. What I mean by revolution is, they have caused changes, whose results are seen in dramatic product and
compute performance. But they have been
done at a very quiet, at a very sustained, and yet influential level. I hope to describe this to you in the
next couple of slides. Up to the 1990s, the role of a package was
just to encapsulate silicon, and protect it from
the environment. But even in the
beginning of the 1990s, it was very clear
that you needed a lot more interconnect from the die or the silicon
to the motherboard, and the package was the medium. In the 1990s, Intel introduced the first
flip-chip organic package. What this really means
is that you are able to connect the entire surface
area of the silicon, as opposed to the previous
implementations where you connected the periphery
of the die using wire bonds. The other thing Intel also did was it moved packaging from being ceramic-based to an organic-based
packaging technology. The value of this
is that in organic, you could process the package
at a lower temperature, and the interconnects in the package were
based on copper, which is a better
interconnect than copper tungsten that was
used in ceramic packages, and an entire new packaging
industry was born. Intel continue this trend
along with other people in the field and took the copper wiring interconnect
in the back of silicon, and extended it through copper
pillar bumps to connect to the package and lead
the industry in enabling fully lead-free
and halogen-free packages. These changes are
tremendous because they allow you to be significantly
environmentally friendly, and reduce contamination
in landfills. Additionally, Intel enabled
land grid array sockets, they improved cost and
improved performance. By encouraging the
greater adoption of ball grid arrays made
small and thin packages, and hence small
and thin laptops, and handheld devices possible. The handheld revolution,
the laptop revolution was a great deal to the thinness
introduced by packaging. By the 2010s, it was very clear
that you needed to do even more interconnect
density scaling. In other words, the die had to be connected to the package, and the package had to be
connected to the motherboard, with significantly
higher densities, which means you had
to shrink the pitch, bring the interconnects closer. The 2010s saw multiple
breakthroughs in the so-called 2D
multi-chip packaging. Technologies like Emeco was focused were introduced
in the market. Memory technologies like HBM, stacking technologies
like Foveros and SOIC opened up the
third dimension, and performance continued
to improve tremendously. All of this is under the root of a basic idea called
heterogeneous integration. What does heterogeneous
integration mean? It means that you
separately manufacture, and you separately test
different components, and then you stitch them on a package to get a higher
level of integration. The basic definition of
heterogeneous integration is when different IP
are implemented on different pieces of
silicon so that they are optimized to work best
on that silicon process, and then you use the package
to stitch them together. In the aggregate when
you bring them together, you get enhanced functionality, and you get much better, improved operating
characteristics. In 2005, I worked
with Bill Holt, who was then the
general manager of the technology and
manufacturing group at Intel, to develop a talk at a conference in San
Francisco called InterPACK. Bill made a few salient points in that talk which are
still relevant today. If you have IP that can be implemented on the same silicon, that's called
homogeneous integration. The best platform to
integrate this is the silicon because it
follows Moore's Law and it allows you to
shrink much more rapidly, and much more systematically
than anything known. If, however, you
want to integrate heterogeneous components to complement homogeneous
components, the package is the ideal
platform to do this. This fact is true,
was true then, is true now, and
will continue to be true in the foreseeable future. Intel had a long
history of using heterogeneous integration
for what is called time-to-market as in to get a
product into market faster. We use to integrate SRAMs on the backend buzz
of a compute die. We also integrated
memory controller apps, both for graphics
as well as memory. These apps were implemented on different processes run
at a different voltage, and were stitched on the package to bring
close to the compute. Where things really took
off was when Intel started integrating DRAM memory
next to the compute. This allowed you to
have a high capacity, reasonably high bandwidth memory sitting right next
to the compute, and this argument has helped
improve compute performance. This proximity of memory has helped to improve
compute performance. As you can see from this slide, the idea of using
heterogeneous integration, and using the package as a compact platform
has been around, and very useful for
quite some time. In conclusion, what
you should take out of this particular
introduction is, historically heterogeneous
integration enabled by packaging has always
enabled better products. Heterogeneous integration
has complimented homogeneous integration
on Moore's Law and will continue to do so. In the past three decades, packaging has steadily improved interconnects and
thermal capability. l just briefly
mentioned it before, but I should also point out
that as performance improves, the total amount
of power that you dissipate also increases, and the package has to have
better and better ability to duct heat out of the package.